 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| SPC21A1 20KB SOUND CONTROLLER GENERAL DESCRIPTION The SPC21A1 is a CPU based two-channel speech/melody synthesizer including CMOS 8-bit microprocessor with 69 instructions, 20K-byte ROM for speech and melody data (Speech is compressed by a 4-bit ADPCM with approx. 6 sec speech duration @ 7KHz sampling rate) and 64-byte working SRAM. It includes two Timer/Counters, 10 Software Selectable I/Os, and one 8-bit current D/A output. For audio processing, melody and speech can be mixed into one output. It operates over a wide voltage range of 2.4V - 5.5V and includes Low Voltage Reset function. The Low Voltage Reset automatically resets when the working voltage is less than 2.2V. In addition, SPC21A1 has a Clock Stop mode for power savings. The power savings mode saves the RAM contents, but freezes the oscillator, causing all other chip functions to be inoperative. The Max. CPU clock frequency is 6.0MHz. It has an Instruction Cycle Rate of 2 clock cycles (min.) - 6 clock cycles (max.). The SPC21A1 includes, not only the latest technology, but also the full commitment and technical support of Sunplus. FEATURES 8-bit microprocessor Provides 20K-byte ROM for program and audio data 64-byte working SRAM Software-based audio processing Wide operating voltage: 2.4V - 3.4V @ 4.0MHz 3.6V - 5.5V @ 6.0MHz Supports Rosc only Max. CPU clock: 4.0MHz @ 3V, 6.0MHz @ 5V Standby mode (Clock Stop mode) for power Savings. Max. 2 A @ 5V 500ns instruction cycle time @ 4.0MHz CPU clock Provides 10 general I/Os Two 12-bit timer/counters 6 INT sources Key wake -up function Approx. 6 sec speech @ 7KHz sampling rate with ADPCM One D/A output Low Voltage Reset BLOCK DIAGRAM 8-bit microprocessor 20K-byte ROM Two Timers TimeBase INT control 64-byte SRAM One 8-bit D/A (current) XI CLK OSC Low Voltage Reset AUD 10 PINS GENERAL I/O PORT IOD5-0 (I/O) IOC3-0 (I/O) APPLICATION FIELD Intelligent education toys Ex. Pattern to voice (animal, car, color, etc.) Spelling (English or Chinese) Math High end toy controller Talking instrument controller General speech synthesizer Industrial controller Sunplus Technology Co., Ltd. 1 Rev.: 1.1 1999.11.19 SPC21A1 FUNCTION DESCRIPTIONS CPU The SPC21A1 8-bit microprocessor is a high performance processor equipped with Accumulator, Program Counter, X Register, Stack pointer and Processor Status Register (this is the same as the 6502 instruction structure). SPC21A1 is able to perform with 6.0MHz (max.) depending on the application specifications. ROM AREA The SPC21A1 provides a 20K-byte ROM that can be defined as the program area, audio data area, or both. RAM AREA The SPC21A1 total RAM consists of 64-bytes (including Stack) at locations from $C0 through $FF. MAP OF MEMORY AND I/Os *I/O PORT: - PORT IOC IOD $0004 $0005 $000C0 USER RAM and STACK $00100 UNUSED $00200 *INT SOURCE: - INTA (from TIMER A) - INTB (from TIMER B) - CPU CLK / 1024 - CPU CLK / 8192 - CPU CLK / 65536 - EXT INT $07000 USER`S PROGRAM & DATA AREA $07FFF $03FFF DUMMY AREA $00600 USER'S PROGRAM & DATA AREA SUNPLUS TEST PROGRAM *MEMORY MAP (From ROM view) $00000 Hardware register, I/Os - I/O CONFIG $0000 $0001 *NMI SOURCE: - INTA (from TIMER A) Sunplus Technology Co., Ltd. 2 Rev.: 1.1 1999.11.19 SPC21A1 I/O PORT CONFIGURATION* Input/Output IOC port : IOC3 - IOC0 logic_2 control output data buffer or OD-NMOS VDD 60K input data OD : Open Drain Input/Output IOD port : IOD3 - IOD0 input data OD-PMOS or buffer Input/Output IOD port : IOD5 - IOD4 input data OD-PMOS or buffer output data logic_3 control OD : Open Drain output data 60K logic_4 control OD : Open Drain 60K *Values shown are for VDD = 5.0V test conditions only. Sunplus Technology Co., Ltd. 3 Rev.: 1.1 1999.11.19 SPC21A1 POWER SAVINGS MODE The SPC21A1 provides a power savings mode (Standby mode) for those applications that require very low stand-by current. To enter standby mode, the Wake-Up Register should be enabled and then stop the CPU In such a mode, clock by writing the STOP CLOCK Register. The CPU will then go to the stand-by mode. RAM and I/Os will remain in their previous states until being awakened. source in the SPC21A1. Port IOD7-0 is the only wake-up After the SPC21A1 is awakened, the internal CPU will go to the RESET State (Tw 65536 x T1) and then continue processing the program. Wakeup Reset will not affect RAM or I/Os (FIG.1). Sleep T1 CPU CLK Reset Wake-up Tw FIG. 1 T1 = 1 / ( FCPU ), Tw 65536 x T1 LOW VOLTAGE RESET The SPC21A1 includes a Low Voltage Reset (LVR) function. Below the minimum power-supply voltage of 2.2V, the CPU system will become unstable and malfunction. Low Voltage Reset will reset all functions into the initial operational (stable) state if the VDD power-supply voltage drops below 2.2V (FIG.2). T1 CPU CLK VDD 2.2V T2 RESET T2 TW A 2 * T1 (The LVR function is the same as Power ON Reset or External Reset.) FIG. 2 Sunplus Technology Co., Ltd. 4 Rev.: 1.1 1999.11.19 SPC21A1 TIMER/COUNTER The SPC21A1 contains two 12-bit timer/counters, TMA and TMB respectively. TMA can be specified as a timer or a counter, but TMB can only be used as a timer. In the timer mode, TMA and TMB are re-loaded upcounters. When timer overflows from $0FFF to $0000, the carry signal will make the timer automatically reload to the user's pre-set value and be up-counted again. At the same time, the carry signal will generate the INT signal if the corresponding bit is enabled in the INT ENABLE Register. If TMA is specified as a counter, users can reset by loading #0 into the counter. After the counter has been activated, the value of the counter can also be read from the counters at the same time. The read instruction will not affect the value of the counter or reset it. Clock source of Timer/Counter can be selected as follows: Timer/Counter TMA 12-BIT TIMER 12-BIT COUNTER TMB 12-BIT TIMER Clock Source CPU CLOCK (T) or T/4 T/64, T/8192, T/65536 or EXT CLK T or T/4 TMA only, select timer or counter Select T or T/4 MODE SELECT REGISTER TIMER CLOCK SELECTOR SPEECH AND MELODY Since the SPC21A1 provides a large ROM and wide range of CPU operation speeds, it is most suitable for speech and melody synthesis. For speech synthesis, the SPC21A1 can provide NMI for accurate sampling frequency. Users can record or synthesize the sound and digitize it into the ROM. The sound data can be played back in the sequence of the control functions as designed by the user's program. Several algorithms are recommended for high fidelity and compression of sound including PCM, LOG PCM, and ADPCM. For melody synthesis, the SPC21A1 provides the dual tone mode. After selecting the dual tone mode, users only need to fill either TMA or TMB, or both TMA and TMB to generate expected frequency for each channel. The hardware will toggle the tone wave automatically without entering into an interrupt service routine. Users are able to simulate musical instruments or sound effects by simply controlling the envelope of tone output. Sunplus Technology Co., Ltd. 5 Rev.: 1.1 1999.11.19 SPC21A1 PIN DESCRIPTION* Mnemonic VDD VSS XI PIN No. 8 7 9 Type I I I Supply voltage input Ground Oscillator crystal input or RESISTOR (Resistor should be connected to VDD) RESET TEST AUD 2 11 10 I I O RESET TEST MODE AUDIO OUTPUT Port C is an 4-bit bi-directional programmable Input / Output port with IOC0 IOC1 IOC2 IOC3 6 5 4 3 I/O I/O I/O I/O Pull-high or Open-drain option. the Pure or Pull-high states. As inputs, Port C can be in either Description As outputs Port C can be a Buffer or Open-drain NMOS type (sink current). IOC1:EXT INT IN IOC2:EXT COUNT IN **See note 1 and 2 below. Port D is an 6-bit bi-directional programmable Input / Output port with IOD0 IOD1 IOD2 IOD3 IOD4 IOD5 17 16 15 14 13 12 I/O I/O I/O I/O I/O I/O Pull-low or Open-drain option. or Pull-low states. As inputs, Port D can be either Pure As outputs, Port D can be either Buffer or Open- drain PMOS type (send current). (Key change, Wake up I/O) **See note 1 and 2 below. * Refer to SPC Programming Guide for complete information. **Note: 1.) Two input states can be specified; Pure Input, Pull-High or Pull Low. 2.) Three output states can be specified as Buffer output, Open Drain PMOS output (send), or Open Drain NMOS output (sink). ABSOLUTE MAXIMUM RATINGS Characteristics DC Supply Voltage Input Voltage Range Operating Temperature Storage Temperature Symbol V+ VIN TA TSTO Ratings < 7V -0.5V to V+ + 0.5V 0 -50 to +60 to +150 Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational conditions see AC/DC Electrical Characteristics. Sunplus Technology Co., Ltd. 6 Rev.: 1.1 1999.11.19 SPC21A1 AC CHARACTERISTICS ( TA = 25 Characteristics Symbol ) Limit Min. OSC Frequency FOSC2 4.0 6.0 MHz VDD = 5V Typ. 2.0 Max. 4.0 Unit MHz Test Condition VDD = 3V DC CHARACTERISTICS (TA = 25 C, VDD = 3 V) Characteristics Operating Voltage Operating Current Standby Current Audio output current Input High Level Input Low Level Output High I IOC,IOD Output Sink I IOC,IOD Input Resistor IOD Symbol VDD IOP ISTBY IAUD VIH VIL IOH Limit Min. 2.4 2.0 -1.0 Typ. 1.5 -1.5 Max. 3.4 2.0 2.0 0.8 Unit V mA A mA V V mA Test Condition For 2-battery FCPU = 3.0MHz @ 3V, no load VDD = 3V VDD = 3V,one-channel VDD = 3V VDD = 3V VDD = 3V VOH = 2V VDD = 3V VOL = 0.8V Pull Low VDD = 3V IOL 2.0 - - mA RIN - 110 - Kohm DC CHARACTERISTICS (TA = 25 C, VDD = 5 V) Characteristics Operating Voltage Operating Current Standby Current Audio output current Input High Level Input Low Level Output High I IOC,IOD Output Sink I IOC,IOD Input Resistor IOD Symbol VDD IOP ISTBY IAUD VIH VIL IOH Limit Min. 3.6 3.0 -1.0 Typ. 4.0 -3.0 Max. 5.5 5.0 2.0 0.8 Unit V mA A mA V V mA Test Condition For 3-battery FCPU = 4.0MHz @ 5V, no load VDD = 5V VDD = 5V, one-channel VDD = 5V VDD = 5V VDD = 5V VOH = 4.2V VDD = 5V VOL = 0.8V Pull Low VDD = 5V Rev.: 1.1 1999.11.19 IOL 4.0 - - mA RIN - 60 - Kohm Sunplus Technology Co., Ltd. 7 SPC21A1 The relationship between the Rosc and the FCPU VDD = 3.0V , Ta = 25 4.0 Fosc ( MHz ) 3.0 2.0 1.0 0.0 0 200 400 600 800 Rosc ( Kohms ) Fosc ( MHz ) VDD = 4.5V , Ta = 25 6.0 5.0 4.0 3.0 2.0 1.0 0.0 0 200 400 600 800 Rosc ( Kohm s ) Frequency vs. Temperature Frequency normalized to 25 1.04 Rosc=200Kohms Frequency vs. VDD FCPU/FCPU(25 1.02 1.00 0.98 0.96 0 10 VDD=5.0V 5.0 4.0 3.0 2.0 1.0 0.0 2.0 Fosc ( MHz ) ) Rosc = 100 Kohms Rosc = 200 Kohms 3.0 4.0 5.0 20 30 40 50 60 Temperature ( ) 70 VDD ( Volts ) Operating current vs. Frequency vs. VDD 4 IOP ( mA ) 3 2 1 0 0 1 2 3 4 5 6 Fosc ( MHz ) VDD = 4.5V VDD = 3V Sunplus Technology Co., Ltd. 8 Rev.: 1.1 1999.11.19 SPC21A1 VDD VDD R1 50K 2 RESET IOC3 IOC2 IOC1 IOC0 XI AUD 9 10 R2 150K Speaker Q1 8050 R3 680 C1 RESET 0.1 3 4 5 6 C2 12 13 14 15 16 17 VDD SPC21A1 IOD5 IOD4 IOD3 IOD2 IOD1 IOD0 0.1 APPLICATION CIRCUIT NOTE 8 VDD VSS TEST 1,7 11 Sunplus Technology Co., Ltd. C3 + C4 220 F 0.1 9 Rev.: 1.1 1999.11.19 SPC21A1 Current Mode DAC Speaker Driver C1: 0.1A F ~ 1A F RB1: 680 ~ 1.5K VDD RB1: 10K ~ 50K RB2: 820 ~ 1.5K C1: 0.1A F ~ 1A F 32AA ~ 64A VDD AAA ~ 8A AUD C1 RB1 8050 AUD RB2 RB1 8050 C1 Figure 1 VDD Figure 2 VDD RB1: 2K~10K; C1: 1 A F~10A F RB2: ~1K; C2: ~0.1 A F RB1: 2K~10K; C1: 1 A F~10A F RB2: ~1K; C2: ~0.1 A F RB1 AAA ~ 64A C2 Enable AAA ~ 8A C2 AUD RB2 C1 RB1 8050 AUD RB2 C1 8050 Figure 3 VDD Figure 4 Power RB1: ~ 360AA (Vol) RB2: ~ 4.7A AUD 1N4148 RE1 RB1 0.01A F AAA ~ 64A AUDP 3 6 LM386 5 7 4 220A F + 10 0.1A F 2 8050 RB1 20K Figure 5 Figure 6 Figure 1:The simplest CKT uses with low impedance speaker. It has high operation current, but low cost. Figure 2:It is the same as Figure 1 but a high impedance speaker is used. Figure 3:The CKT contains a low pass filter. It is capable of providing higher speech quality, but it takes higher operation current. Figure 4:Improved version of Figure 3. The standby current can be controlled by the enable pin. Figure 5:The current mirror mode. It is able to control the volume. In addition, it is more stable and has lower operation current than Figure 1-3. Figure 6:High quality, low operation current CKT, but more expensive. Sunplus Technology Co., Ltd. 10 Rev.: 1.1 1999.11.19 SPC21A1 PAD ASSIGNMENT AND LOCATIONS PAD Assignment Chip Size: 1980 m x 1420 m This IC substrate should be connected to VSS Note: To ensure that the IC functions properly, bond all VDD, VSS, AVDD and AVSS pins. Ordering Information Product Number SPC21A1-nnnnV-C Note1: Code number (nnnnV) is assigned for customer. Note2: Code number (nnnn = 0000 - 9999) ; version (A = A - Z). Package Type Chip form NOTE: SUNPLUS TECHNOLOGY CO., LTD reserves the right to make changes at any time without notice in order to improve the design and performance and to supply the best possible product. Sunplus Technology Co., Ltd. 11 Rev.: 1.1 1999.11.19 SPC21A1 PAD Locations Pad No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Pad Name VSS RESET IOC3 IOC2 IOC1 IOC0 VSS VDD XI AUD TEST IOD5 IOD4 IOD3 IOD2 IOD1 IOD0 X -822 -604 -431 -276 -125 30 187 327 482 648 803 788 788 788 788 788 788 Y -509 -498 -509 -509 -509 -509 -509 -509 -498 -498 -498 -316 -157 -6 153 305 464 DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. are for reference purposes only. Please note that application circuits illustrated in this document Sunplus Technology Co., Ltd. 12 Rev.: 1.1 1999.11.19 |
Price & Availability of SPC21A1
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |